Why 2 part CCD chips can suffer SSE Explained

[Ed Hill]

Hi,

I stumbled upon a well written article in Video Systems magazine by Steve Mullen. This clearly explains the electronic characteristics of CCDs and why the SSE effect can happen at low light levels when the dual processors for 1 ccd are not calibrated.

The article is from Nov 2005 but makes the SSE problem understandable from an engineering view.

Ed Hill

http://videosystems.com/mag/video_jv...x.html#sidebar

"All CCDs have a linear transfer function that describes the conversion of input light level to output voltage. A light range of 0 to 100 percent (total saturation) is mapped to 0 to 100 IRE. CCDs may have, at the low end of the light input range, a “nonlinearity” (a tiny step) in the linear function. For example, light levels beginning at 15 percent yield IRE values of 17 to 102 IRE rather than 15 to 100 IRE.

Given the HSTR design of the HD100 chips, there are naturally two transfer functions for each CCD. If the output from one half of the CCD is within a range of a nonlinearity and the other half is not, the difference may be manifest as the right and left sides of the image varying slightly in brightness — the so called Split Screen Effect (SSE).

Initially, the Internet was buzzing with reports of SSE because the initial production units imported only by Region 50 countries had not undergone the advanced calibration process that all HD100 units undergo when imported into the U.S.

Because a nonlinearity is typically only a few IRE, it is not visible when an adequate signal range is input. Under low illumination, as an SSE precaution, I set zebra to 70-80 and then add light and gain so faces or white objects have zebra. If necessary, I set gain at +6dB (when major portions of the image are dark) or +12dB (when the picture contains a minimum of dark areas)."